1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device provided with a plurality of memory cells and data transmission line pairs.
2. Description of the Background Art
Conventionally, a synchronous DRAM (hereinafter referred to as SDRAM) can select one of the three word configurations: x4, x8, and x16. These x4, x8, and x16 word configurations respectively allow simultaneous inputting/outputting of 4 bits of data, 8 bits of data, and 16 bits of data.
In addition, an SDRAM allows the so-called multi-bit test (hereinafter referred to as MBT) that permits the reduction in the testing time and an increase in the number of chips tested at the same time. With MBT, a plurality of memory cells (for instance, four memory cells) can be tested for normalcy via one data input/output pin.
FIG. 24 is a block diagram showing a main portion of such an SRAM. In FIG. 24, SDRAM includes data buses DB0 to DB3 and DB6, selectors 151a to 151d, write data amplifiers (hereinafter referred to as WD amplifiers) 152a to 152d, write buffers 153a to 153d, and global IO line pairs GIO0 to GIO3.
Selectors 151a to 151d connect data bus DB2 to WD amplifiers 152a to 152d during a write operation in x4 configuration, and connect data bus DB0 to WD amplifiers 152a and 152b and connect data bus DB2 to WD amplifiers 152c and 152d during a write operation in x8 configuration. Moreover, selectors 151a to 151d connect data buses DB0 to DB3 respectively to WD amplifiers 152a to 152d during a write operation in x16 configuration, and connect data bus DB2 to WD amplifiers 152b and 152d and connect data bus DB6 to WD amplifiers 152a and 152c during MBT.
WD amplifiers 152a to 152d are respectively activated in response to signals CBS0 to CBS3 attaining the logic high or xe2x80x9cHxe2x80x9d level or the active level, amplify the data provided from outside via data buses DB0 to DB3 and DB6, and apply the amplified data to write buffers 153a to 153d. Write buffers 153a to 153d respectively transmit the data provided from WD amplifiers 152a to 152d to global IO line pairs GIO0 to GIO3.
During a write operation in x4 configuration, one of signals CBS0 to CBS3 (for instance, CBS0) attains the xe2x80x9cHxe2x80x9d level or the active level, and the data provided to data bus DB2 from outside is transmitted to global IO line pair GIO0 via selector 151a, WD amplifier 152a, and write buffer 153a. The data transmitted to global IO line pair GIO0 is written into a selected memory cell.
During a write operation in x8 configuration, one of signals CBS0 and CBS1 (for instance, CBS0) and one of signals CBS2 and CBS3 (for instance, CBS2) attain the xe2x80x9cHxe2x80x9d level or the active level, and the data provided to data bus DB0 from outside is transmitted to global IO line pair GIO0 via selector 151a, WD amplifier 152a, and write buffer 153a, while the data provided to data bus DB2 from outside is transmitted to global IO line pair GIO2 via selector 151c, WD amplifier 152c, and write buffer 153c. The data transmitted to global IO line pairs GIO0 and GIO2 are respectively written into the two selected memory cells.
During a write operation in x16 configuration, signals CBS0 to CBS3 all attain the xe2x80x9cHxe2x80x9d level or the active level, and the data provided to data buses DB0 to DB3 from outside are transmitted to global IO line pairs GIO0 to GIO3 via selectors 151a to 151d, WD amplifiers 152a to 152d, and write buffers 153a to 153d, respectively. The data transmitted to global IO line pairs GIO0 to GIO3 are respectively written into the four selected memory cells.
During a write operation in MBT, signals CBS0 to CBS3 all attain the xe2x80x9cHxe2x80x9d level or the active level, and the data provided to data bus DB2 from outside is transmitted to global IO line pairs GIO1 and GIO3 via selectors 151b and 151d, WD amplifiers 152b and 152d, and write buffers 153b and 153d, while the data provided to data bus DB6 from outside is transmitted to global IO line pairs GIO0 and GIO2 via selector 151a and 151c, WD amplifiers 152a and 152c, and write buffers 153a and 153c. The data transmitted to global IO line pairs GIO0 to GIO3 are respectively written into the four selected memory cells.
In addition, the SDRAM includes preamplifiers 154a to 154d, a CAS latency shifters (hereinafter referred to as CL shifters) 155a to 155d, selectors 156a to 156d and 158a to 158d, and read data buffers (hereinafter referred to as RD buffers) 157a to 157d. 
Preamplifiers 154a to 154d are respectively activated in response to signals PAE0 to PAE3 attaining the xe2x80x9cHxe2x80x9d level or the active level, and amplify the data signals read out to global IO line pairs GIO0 to GIO3. CL shifters 155a to 155d respectively delay the output signals from preamplifiers 154a to 154d by one clock cycle.
During a read operation in x4 configuration, selectors 156a to 156d apply to RD buffer 157c the data provided via CL shifter 155a from one preamplifier (for instance 154a) of preamplifiers 154a to 154d selected by signals PAE0 to PAE3. During a read operation in x8 configuration, selectors 156a to 156d apply to RD buffer 157a the data provided via CL shifter 155a from one preamplifier (for instance 154a) of preamplifiers 154a and 154b selected by signals PAE0 and PAE1, and apply to RD buffers 157c to the data provided via CL shifter 155c from one preamplifier (for instance l54c) of preamplifiers 154c and 154d selected by signals PAE2 and PAE3. During the read operations in x16 configuration and in MBT, selectors 156a to 156d respectively apply to RD buffers 157a to 155d the data provided via CL shifters 155a to 155d from preamplifiers 154a to 154d. 
Selectors 158a to 158d couple RD buffers 157a to 157d to data buses DB0 to DB3 during a normal read operation, and couple RD buffers 157a to 157d respectively to data buses DB6, DB2, DB6, and DB2 during a read operation in MBT.
RD buffers 157a to 157d respectively drive data buses DB0 to DB3 according to data provided from selectors 156a to 156d during a normal read operation, respectively drive data buses DB6, DB2, DB6, and DB2 during a read operation in MBT.
During the read operation in x4 configuration, one of signals PAE0 to PAE3 (for instance, signal PAE0) attains the xe2x80x9cHxe2x80x9d level or the active level, and the data read out on a global IO line pair (in this case, GIO0) is transmitted to data bus DB2 via preamplifier 154a, CL shifter 155a, selector 156c, RD buffer 157c, and selector 158c. The data transmitted to data bus DB2 is output to the outside.
During the read operation in x8 configuration, one of signals PAE0 and PAE1 (for instance, PAE0) attains the xe2x80x9cHxe2x80x9d level or the active level, and the data read out on a global IO line pair (in this case, GIO0) is transmitted to data bus DB0 via preamplifier 154a, CL shifter 155a, selector 156a, RD buffer 157a, and selector 158a, and one of signals PAE2 and PAE3 (for instance, PAE2) attains the xe2x80x9cHxe2x80x9d level or the active level, and the data read out on a global IO line pair (in this case, GIO2) is transmitted to data bus DB2 via preamplifier 154c, CL shifter 155c, selector 156c, RD buffer 157c, and selector 158c. The data transmitted to data buses DB0 and DB2 are output to the outside.
During the read operation in x16 configuration, signals PAE0 to PAE3 all attain the xe2x80x9cHxe2x80x9d level or the active level, and the data read out on global IO line pairs GIO0 to GIO3 are respectively transmitted to data buses DB0 to DB3 via preamplifiers 154a to 154d, CL shifters 155a to 155d, selectors 156a to 156d, RD buffers 157a to 157d, and selectors 158a to 158d. The data transmitted to data buses DB0 to DB3 are output to the outside.
During the read operation in MBT, signals PAE0 to PAE3 all attain the xe2x80x9cHxe2x80x9d level or the active level, and the data read out on global IO line pairs GIO0 to GIO3 are respectively transmitted to data buses DB6, DB2, DB6, DB2 via preamplifiers 154a to 154d, CL shifters 155a to 155d, selectors 156a to 156d, RD buffers 157a to 157d, and selectors 158a to 158d. The data transmitted to data buses DB0 to DB3 are output to the outside. When the 2 bits of data read out on data bus DB6 match, the two memory cells are determined as being normal, and when no match occurs, the memory cells are determined as being defective. When the 2 bits of data read out on data bus DB2 match, the two memory cells are determined as being normal, and when no match occurs, the memory cells are determined as being defective.
The portion relating to reading of data in the block shown in FIG. 24 will be described in detail below.
Preamplifier 154c includes P-channel MOS transistors 161 to 165 and N-channel MOS transistors 166 to 168 as shown in FIG. 25. Input/output nodes N161 and N162 in preamplifier 154c are respectively connected to global IO lines GIOL2 and /GIOL2. P-channel MOS transistors 161 and 162 are connected in series between nodes N161 and N162, and receive signal ZPAEQ at their respective gates. P-channel MOS transistors 161 and 162 form an equalizer. When signal ZPAEQ attains the xe2x80x9cLxe2x80x9d level or the active level, P-channel MOS transistors 161 and 162 are rendered conductive, and nodes N161 and N162 are equalized to the xe2x80x9cHxe2x80x9d level.
P-channel MOS transistor 163 is connected between a power-supply potential VCC line and a node N163. P-channel MOS transistor 164 is connected between node N163 and node N161, and P-channel MOS transistor 165 is connected between node N163 and node N162, respectively. N-channel MOS transistor 166 is connected between node N161 and node N168 and N-channel MOS transistor 167 is connected between node N162 and node N168, respectively. P-channel MOS transistor 168 is connected between node N168 and a ground potential VSS line. Gates of MOS transistors 163 and 168 receive signals ZPAE2 and PAE2, respectively. Gates of MOS transistor transistors 164 and 166 are both connected to node N162, and gates of MOS transistors 165 and 167 are both connected to node N161. MOS transistors 163 to 168 form a differential amplifier. This differential amplifier is activated in response to signals ZPAE2 and PAE2 respectively attaining the xe2x80x9cLxe2x80x9d level and the xe2x80x9cHxe2x80x9d level, causing either node N161 or node N162 having the higher potential to attain the xe2x80x9cHxe2x80x9d level while causing the other node to attain the xe2x80x9cLxe2x80x9d level. Signals appearing on nodes N161 and N162 become output signals PDCL and /PDCL from preamplifier 154c. 
During a read operation, signal ZPAEQ rises to the xe2x80x9cHxe2x80x9d level or the inactive level, rendering P-channel MOS transistors 161 and 162 non-conductive, and thus the equalization of nodes N161 and N162 is interrupted. Thereafter, data is read from a selected memory cell, and slight potential difference is created between global IO lines GIOL2 and /GIOL2 according to the data. Then, signals PAE and ZPAE respectively attain the xe2x80x9cHxe2x80x9d level and the xe2x80x9cLxe2x80x9d level, activating the differential amplifier formed by MOS transistors 163 to 168 so that, of global IO lines GIOL2 and /GIOL2, the one having the higher potential is brought to the xe2x80x9cHxe2x80x9d level (power-supply potential VCC), and the one having the lower potential is brought to the xe2x80x9cLxe2x80x9d level (ground potential VSS).
Other preamplifiers 154a, 154b, and 154d have the same configuration as the configuration of preamplifier 154c. Preamplifiers 154a, 154b, and 154d, however, are provided with signals PAE0 and ZPAE0, signals PAE1 and ZPAE1, and signals PAE3 and ZPAE3, respectively, instead of signals PAE2 and ZPAE2.
Preamplifier activating signals PAE0 to PAE3 are generated based on a preamplifier activating master signal PACM and column block decode signals CBS0 to CBS3, as shown in FIG. 26.
CL shifter 155c includes a master latch circuit 169 and a slave latch circuit 170, as shown in FIG. 25. Latch circuit 169 and 170 invert output signals PDCL and /PDCL from preamplifier 154c and output the inverted signals with a delay of one clock cycle. Output signals PD2 and ZPD2 from slave latch circuit 170 are applied to selector 156c. Other CL shifters 155a, 155b, and 155d have the same configuration as CL shifter 155c. 
Selector 156c includes P-channel MOS transistors 175 and 176, N-channel MOS transistors 181 to 188, and N-channel MOS transistors 191 to 198, as shown in FIG. 27. P-channel MOS transistor 175 is connected between a power-supply potential VCC line and an output node N175 and P-channel MOS transistor 176 is connected between power-supply potential VCC line and an output node N176, respectively. P-channel MOS transistor 175 and 176 receive a signal RDRVM at their respective gates. N-channel MOS transistors 181 and 182, N-channel MOS transistors 183 and 184, N-channel MOS transistors 185 and 186, and N-channel MOS transistors 187 and 188 are respectively connected in series between node N175 and a ground potential VSS line. N-channel MOS transistors 191 and 192, N-channel MOS transistors 193 and 194, N-channel MOS transistors 195 and 196, and N-channel MOS transistors 197 and 198 are respectively connected in series between node N176 and ground potential VSS line.
Gates of N-channel MOS transistors 181, 183, 185, and 187 respectively receive signals PD0 to PD3, and gates of N-channel MOS transistors 191, 193, 195, and 197 respectively receive signals ZPD0 to ZPD3. Gates of N-channel MOS transistors 182, 184, 192, and 194 all receive a signal RDRV4. Gates of N-channel MOS transistors 186 and 196 both receive a signal RDRV4816. Gates of N-channel MOS transistors 188 and 198 both receive a signal RDRV48. Signals that appear on nodes N175 and N176 become signals ZDRV and ZZDRV, respectively.
Signal RDRV4 attain the xe2x80x9cHxe2x80x9d level or the active level during the read operation in x4 configuration. Signal RDRV48 attains the xe2x80x9cHxe2x80x9d level or the active level during the read operations in x4 configuration and x8 configuration. Signal RDRV4816 attain the xe2x80x9cHxe2x80x9d level or the active level during the read operations in x4 configuration, x8 configuration, x16 configuration, and MBT.
During the read operation in x4 configuration, signal RDRVM first attain the xe2x80x9cLxe2x80x9d level for a prescribed period of time, rendering P-channel MOS transistors 175 and 176 conductive for the prescribed period of time, and nodes N175 and N176 are precharged to the xe2x80x9cHxe2x80x9d level. Thereafter, signals RDRV4, RDRV48, RDRV4816 attain the xe2x80x9cHxe2x80x9d level or the active level, rendering N-channel MOS transistors 182, 184, 186, 188, 192, 194, 196, and 198 conductive, while one of signals PD0 to PD3 and ZPD0 to ZPD3 (for instance, PD3) attains the xe2x80x9cHxe2x80x9d level, rendering an N-channel MOS transistor (in this case, 187) conductive, and thus node N175 attains the xe2x80x9cLxe2x80x9d level.
During the read operation in x8 configuration, after nodes N175 and N176 are precharged to the xe2x80x9cHxe2x80x9d level, signals RDRV48 and RDRV4816 attain the xe2x80x9cHxe2x80x9d level or the active level, rendering N-channel MOS transistors 186, 188, 196, and 198 conductive, while one of signals PD2, PD3, ZPD2, and ZPD3 (for instance, PD2) attains the xe2x80x9cHxe2x80x9d level, rendering an N-channel MOS transistor (in this case, 185) conductive, and thus node N175 attains the xe2x80x9cLxe2x80x9d level.
During the read operation in x16 configuration and MBT, after nodes N175 and N176 are precharged to the xe2x80x9cHxe2x80x9d level, signal RDRV4816 attains the xe2x80x9cHxe2x80x9d level or the active level, rendering N-channel MOS transistors 186 and 196 conductive, while one of signals PD2 and ZPD2 (for instance, PD2) attains the xe2x80x9cHxe2x80x9d level, rendering an N-channel MOS transistor (in this case, 185) conductive, and thus node N175 attains the xe2x80x9cLxe2x80x9d level.
Signals RDRV4, RDRV48, RDRV4816 are generated by NAND gates 201 to 203 and inverters 204 to 206 based on signal RDRVM and word configuration selecting signals Mx4, Mx48, and Mx4816, as shown in FIG. 28. Thus, NAND gate 201 receives signals RDRVM and Mx4, and the output signal from NAND gate 201 is inverted by inverter 204 and becomes signal RDRV4. NAND gate 202 receives signals RDRVM and Mx48, and the output signal from NAND gate 202 is inverted by inverter 205 and becomes signal RDRV48. NAND gate 203 receives signals RDRVM and Mx4816, and the output signal from NAND gate 203 is inverted by inverter 206 and becomes signal RDRV4816. Signal Mx4 attains the xe2x80x9cHxe2x80x9d level in x4 configuration. Signal Mx48 attains the xe2x80x9cHxe2x80x9d level in x4 configuration and x8 configuration. Signal Mx4816 attains the xe2x80x9cHxe2x80x9d level in x4 configuration, x8 configuration, and x16 configuration.
Other selectors 156a, 156b, and 156d have the same configuration as the configuration of selector 156c. Signal RDRV816 instead of signal RDRV4, however, is input to gates of N-channel MOB transistors 182 and 192, and signal RDRV8 instead of signal RDRV4 is input to gates of N-channel MOS transistors 184 and 194, and the gates of N-channel MOS transistors 186, 188, 196, and 198 are grounded. Signal RDRV816 attains the xe2x80x9cHxe2x80x9d level or the active level during the read operations in x8 configuration, x16 configuration, while signal RDRV8 attains the xe2x80x9cHxe2x80x9d level or the active level during the read operations in x8 configuration and MBT.
In selector 156b, signal RDRV16 instead of signal RDRV4 is input to the gates of N-channel MOS transistors 184 and 194, and the gates of N-channel MOS transistors 182, 186, 188, 192, 196, and 198 are grounded. Signal RDRV16 attains the xe2x80x9cHxe2x80x9d level or the active level during the read operations in x16 configuration and MBT. In selector 156d, signal RDRV16 instead of signal RDRV48 is input to the gates of N-channel MOS transistors 188 and 198, and the gates of N-channel MOS transistors 182, 184, 186, 192, 194, and 196 are grounded.
RD buffer 157c includes inverters 211 to 214, NOR gates 215 and 216, P-channel MOS transistors 217 and 218, and N-channel MOS transistors 219 and 220, as shown in FIG. 29. It is assumed that RD buffer 157c is connected to data bus DB2 by selector 158c. 
P-channel MOS transistors 217 and 218 are connected between a power-supply potential VCC line and data bus lines DBL2 and /DBL2, respectively, and receive signals ZDRV and ZZDRV from selector 156c respectively at their gates. N-channel MOS transistors 219 and 220 are connected between a ground potential VSS line and data bus lines DBL2 and /DBL2, respectively. NOR gate 215 receives signals TE and ZZDRV, and an output signal xcfx86215 from NOR gate 215 is input to a gate of N-channel MOS transistor 219. NOR gate 216 receives signals TE and ZDRV, and an output signal xcfx86216 from NOR gate 216 is input to a gate of N-channel MOS transistor 220. Inverters 211 and 212 form a latch circuit which latches the level of signal ZDRV. Inverters 211 and 212 form a latch circuit which latches the level of signal ZZDRV. Other RD buffers 157a, 157b, 157d have the same configuration as RD buffer 157c. 
FIG. 30 is a circuit diagram showing an equalizer 221 provided to a data bus DB2. In FIG. 30, equalizer 221 includes N-channel MOS transistors 222 to 224. N-channel MOS transistors 222 and 223 are connected between data bus lines DBL2 and /DBL2 and a ground potential VSS line, respectively, and N-channel MOS transistor 224 is connected between data bus lines DBL2 and /DBL2. N-channel MOS transistor 222 to 224 receive a signal DBEQ at their gates. When signal DBEQ attains the xe2x80x9cHxe2x80x9d level or the active level, N-channel MOS transistors 222 to 224 are rendered conductive, and data bus lines DBL2 and /DBL2 are equalized to the xe2x80x9cLxe2x80x9d level (ground potential VSS). Equalizer 221 is provided to each of data buses DB0 to DB3 and DB6.
FIG. 31 is a timing chart illustrating the normal read operations of RD buffer 157c shown in FIG. 29 and equalizer 221 shown in FIG. 30. As shown in FIG. 31, signal TE is fixed to the xe2x80x9cLxe2x80x9d level during a normal read operation. Thus, NOR gates 215 and 216 respectively operate as inverters for signals ZZDRV and ZDRV. In the initial state, signals ZDRV and ZZDRV are at the xe2x80x9cHxe2x80x9d level, and MOS transistors 217 to 220 are all rendered non-conductive. Moreover, the equalization is complete and N-channel MOS transistors 222 to 224 are non-conductive, and data bus lines DBL2 and /DBL2 are both at the xe2x80x9cLxe2x80x9d level and in the high impedance state.
At a point in time, when the data is read out from a memory cell, and signal ZDRV attains the xe2x80x9cLxe2x80x9d level, for instance, MOS transistors 217 and 220 are rendered conductive, and data bus lines DBL2 and /DBL2 respectively attain the xe2x80x9cHxe2x80x9d level and the xe2x80x9cLxe2x80x9d level. The potentials of data bus lines DBL2 and /DBL2 are compared, and a signal of the level corresponding to the result of the comparison is output as read data to the outside.
FIG. 32 is a timing chart illustrating the read operations in MBT of RD buffer 157c shown in FIG. 29 and equalizer 221 shown in FIG. 30. In MBT, RD buffer 157c is connected to data bus DB6 by selector 158c. As shown in FIG. 32, signal TE is fixed to the xe2x80x9cHxe2x80x9d level during MBT. Thus, output signals xcfx86215 and xcfx86216 from NOR gates 215 and 216 attain the xe2x80x9cLxe2x80x9d level, and N-channel MOS transistors 219 and 220 are fixed in the non-conductive state. In the initial state, signals ZDRV and ZZDRV are at the xe2x80x9cHxe2x80x9d level, and P-channel MOS transistors 217 and 218 are rendered non-conductive. Moreover, the equalization is complete and N-channel MOS transistors 222 to 224 are non-conductive, and data bus lines DBL6 and /DBL6 are both at the xe2x80x9cLxe2x80x9d level and in the high impedance state.
At a point in time, when the data is read out from a memory cell, and signal ZDRV attains the xe2x80x9cLxe2x80x9d level, for instance, MOS transistor 217 alone among MOS transistors 217 and 220 is rendered conductive, and data bus line DBL6 attains the xe2x80x9cLxe2x80x9d level. Data bus line /DBL6 remains unchanged at the xe2x80x9cLxe2x80x9d level and in the high impedance state. At this time, data bus DB6 is driven also by RD buffer 157a. During a write operation in MBT, same data is written into two memory cells from data bus DB6 via selector 151a and 151c, WD amplifiers 152a and 152c, write buffers 153a and 153c, and global IO line pairs GIO0 and GIO2.
During the read operation in MBT, if two memory cells are normal, the same data is read out on global IO line pairs GIO0 and GIO2, and only one of data bus lines DBL6 and /DBL6 (for instance, DBL6) is brought to the xe2x80x9cHxe2x80x9d level. If one of the two memory cell is defective, however, different data are read out on global IO line pairs GIO0 and GIO2, and both data bus lines DBL6 and /DBL6 are brought to the xe2x80x9cHxe2x80x9d level. Thus, the normalcy of two memory cells can be determined from the comparison of the levels of data bus lines DBL6 and /DBL6, and a signal of the level corresponding to the result of the determination is output to the outside.
A conventional SDRAM configured in the above-described manner has a problem that, since global IO line pairs GIO0 to GIO3 are directly connected to input/output nodes N161 and N162 of preamplifiers 154a to 154d, the equalization of global IO line pairs GIO0 to GIO3 becomes insufficient causing the read operation to become unstable when a high-speed operation is attempted.
In addition, a conventional SDRAM has a problem of complicated layout and a large layout area since selectors 156a to 156d are provided between CL shifters 155a to 155d and RD buffers 157a to 157d. 
Moreover, there is a problem of large current consumption since each of data bus lines DBL and /DBL are driven to a power-supply potential VCC or a ground potential VSS.
Thus, the main object of the present invention is to provide a semiconductor memory device capable of a stable read operation and requiring small layout area and small current consumption.
According to one aspect of the present invention, a switching element pair connected between the other end of a data transmission line pair and an input/output node pair of a preamplifier and rendered conductive in a pulsed manner for a prescribed period of time to provide a potential difference produced between the data transmission line pair to the input/output node pair of the preamplifier is provided. Since the equalization of the data transmission line pair can be started immediately after the switching element pair is rendered conductive in a pulsed manner, longer equalization period can be set aside for the data transmission line pair having a large capacity so that the read operation can be stabilized.
Preferably, a first equalizer for equalizing potentials of the data transmission pair to a prescribed precharge potential during a first equalization period after the switching element pair is rendered conductive in a pulsed manner and a second equalizer for equalizing potentials of the input/output node pair of the preamplifier to the prescribed precharge potential during a second equalization period before the switching element pair is rendered conductive in a pulsed manner are further provided. Thus, the equalization of the data transmission line pair and the equalization of the input/output node pair of the preamplifier can be effected separately.
Preferably, the memory array and the data transmission line pair are provided in plurality, and a selecting circuit for selecting one of a plurality of the data transmission line pairs according to an address signal and for rendering conductive in a pulsed manner a switching element pair corresponding to the selected data transmission line for the above prescribed period of time is provided. In this case, of the plurality of data transmission line pairs, only the data transmission line pair designated by the address signal is connected in a pulsed manner to an input/output node pair of a preamplifier.
Preferably, a first equalizer for equalizing potentials of each data transmission pair to a prescribed precharge potential during a first equalization period after the other end of the data transmission line and the input/output node pair of the preamplifier are connected in a pulsed manner and a second equalizer for equalizing potentials of the input/output node pair of the preamplifier to the prescribed precharge potential during a second equalization period before the other end of the data transmission line and the input/output node pair of the preamplifier are connected in a pulsed manner are further provided. Thus, the equalization of each data transmission line pair and the equalization of the input/output node pair of the preamplifier can be effected separately.
According to another aspect of the present invention, selectors for respectively connecting other ends of N data transmission line pairs with input/output node pairs of N preamplifiers in a first read mode and for selecting M data transmission line pairs out of N data transmission line pairs according to an address signal and connecting other ends of selected M data transmission line pairs respectively to input/output node pairs of pre-selected M preamplifiers in a second read mode are provided. Thus, the layout can be simplified and the layout area can be reduced in comparison with the conventional example in which the selectors are provided between N preamplifiers and N transmission circuits.
Preferably, a determination circuit for determining in a test mode whether output data signals of N preamplifiers match in logic, and for outputting a signal indicating the normalcy of the selected N memory cells when a match occurs and outputting a signal indicating at least one memory cell of the selected N memory cells as being defective when no match occurs is further provided. In this case, N memory cells can be tested for normalcy at the same time.
According to a further aspect of the present invention, a first drive circuit for providing in a pulsed manner for a prescribed period of time a first potential and a second potential respectively to one end of a first data transmission line and to one end of a second data transmission line contained in a data transmission line pair to bring the first and second data transmission lines respectively to a third potential and a fourth potential between the first and second potentials when the data read by a read circuit is of a first logic, and for providing in a pulsed manner for said prescribed period of time the second and first potentials respectively to one end of the first data transmission line and to one end of the second data transmission line to bring the first and second data transmission lines respectively to the fourth and third potentials when the data read by the read circuit is of a second logic is provided. Thus, the consumed current can be kept small in comparison with the conventional example in which each of the first and second data transmission lines is brought to the first potential or the second potential.
Preferably, the first drive circuit includes a delay circuit having a plurality of inverters which are connected in series and each of which is driven by a power-supply voltage, and the above prescribed period of time is the time period required from the time when a signal synchronized to a read operation of the read circuit is input to the delay circuit to the time when the signal is output from the delay circuit. In this case, when the power-supply potential is lowered, the delay time of the delay circuit is increased and the charging/discharging time of the data transmission lines becomes longer so that the potential amplitudes of the first and second data transmission lines are kept from becoming smaller due to the lowering of the power-supply potential.
Preferably, an equalizer for equalizing potentials of the first and second data transmission lines to a prescribed precharge potential between the first and second potentials during an equalization period before the first and second potentials are provided to the first and second data transmission lines is further provided. In this case, the read operation can be stabilized.
Preferably, the equalizer includes a diode element, and a connecting circuit for connecting the diode element between the first and second data transmission lines and a line having the second potential during the equalization period. In this case, a precharging power source is not required so that the configuration can be simplified.
Preferably, the equalizer is provided in plurality, and the plurality of equalizers are scatteringly provided in a direction in which the first and second data transmission lines extend. In this case, a high-speed equalization of the first and second data transmission lines can be achieved.
Preferably, a sub-equalizer for connecting the first data transmission line and the second data transmission line during the equalization period is further provided. In this case, the equalization of the first and second data transmission lines can be achieved at a higher speed.
Preferably, the sub-equalizer is provided in plurality, and the plurality of sub-equalizers are scatteringly provided in a direction in which the first and second data transmission lines extend. In this case, the equalization of the first and second data transmission lines can be achieved at an even higher speed.
Preferably, a control circuit for activating all of the plurality of sub-equalizers in the test mode and for activating only a pre-selected sub-equalizer of the plurality of sub-equalizers during a normal operation is further provided. In this case, the equalization period for the normal operation and for the test mode can be made the same.
Preferably, a second drive circuit activated in the test mode, for causing the first data transmission line to attain the first potential when data read out by the read circuit is of a first logic and for causing the second data transmission line to attain the first potential when the data is of a second logic, and a determination circuit for determining the normalcy of a selected memory cell, based on potentials of the first and second data transmission lines are further provided. In this case, each of the first and second data transmission lines are brought to the precharge potential or the first potential so that the testing operation can be stabilized.